Replacement metal gate transistor processing relies on the encapsulation of a dummy gate material in a dielectric fill. See, for example, U.S. Pat. No. 7,923,337, issued to Chang et al., entitled “Fin Field Effect Transistor Devices with Self-Aligned Source and Drain Regions,” the entire contents of which are incorporated by reference herein.
The dielectric fill serves both a structural and electrical purpose. Specifically, the dielectric fill allows for the selective removal of the dummy gate material. The dielectric fill is also used to insulate between the source/drain (S/D) contact and the gate electrode.
When the dielectric material is deposited around the dummy gates, keyholes, air gaps or voids can be formed in the dielectric in the spaces between the dummy gates. The formation of keyholes during the dielectric deposition process can be a major problem in replacement metal gate processes. Namely, unwanted keyholes can provide a path for the formation of parasitic metal “stringers” which can short out adjacent devices or circuits unintentionally. In some instances, keyhole formation might be desirable. See, for example, U.S. Pat. No. 6,033,981 issued to Lee et al., entitled “Keyhole-free process for high aspect ratio gap filling,” which describes how these air gaps or keyholes might be helpful or harmful depending on the situation.
Therefore, fabrication techniques that leverage the helpful aspects of keyhole formation exclusive of the harmful aspects would be desirable.